Flash memory electrically erasable programmable read only memory (EEPROM) devices are electrically erasable non-volatile memory devices fabricated with tunnel oxides and high voltage transistors for programming and erasing the devices.
Flash EEPROM cells are typically formed by growing a thin oxide on a substrate, then depositing a first layer of doped polysilicon or amorphous silicon and etching the first layer to form the floating gate of the memory cell. Next, a dielectric material, such as an oxide-nitride-oxide (ONO) layer is deposited over the entire substrate, and a second layer of doped polysilicon or amorphous silicon is deposited on the dielectric layer. The second layer of doped polysilicon or amorphous silicon forms the control gate of the memory cell. The dielectric layer and the second layer are then etched to form the stacked gate structure of the memory cell.
One problem with the above-described process is that the floating gate makes the topography of the substrate uneven. Thus, when the dielectric layer and the second polysilicon or amorphous silicon layer are deposited, portions of these layers are thicker in some areas and thinner in others. The uneven thickness of these layers makes the process of lithographic patterning and etching of the second polysilicon or amorphous silicon layer and the dielectric layer difficult. As a result, incomplete etching can result along the thicker portions of these layers and overetching along the thinner portions.
There is a need, therefore, for an improved method of fabricating a flash memory cell. In particular, the process should facilitate the etch process of the control gate and dielectric layers.